(r7) IfpacDocumentation < Palomar/ZTF

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---+ IFPAC System Documentation
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%RED% *Red* %ENDCOLOR% - Document empty <br>
<font color="#ffcc00"> *Yellow* </font> - Document in progress <br>
%GREEN% *Green* %ENDCOLOR% - Document completed <br>

---+++++ Hardware
   * *Single Board Controller*
      * *Single Board Controller Overview*
         * %RED% Single Board Controller Layout Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Functional block placement (clock functions, bias functions, and signal chain)
            * Ground plane layout and analysis
            * Configuration Control
            * Power consumption
            * Board temperature gradients and thermal analysis
      * *Clock Driver*
         * %RED% Clock Driver Schematic Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * All clock channels
         * %RED% Clock Driver Design Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Clock voltage range
            * Clock voltage resolution
            * Clock voltage noise analysis
            * Switching speed analysis
            * Clock driver amplifier design
            * Driving current and load analysis
            * Required voltages
            * Power Supply Noise Requirements (PSRR Analysis)
            * Power consumption
            * Thermal Analysis
            * Heat dissipation/Thermal analysis
      * *Bias Voltages*
         * %RED% Bias Voltage Schematic Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * All bias channels
         * %RED% Bias Voltage Design Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Bias voltage range
            * Bias voltage resolution
            * Bias voltage noise analysis
            * Bias voltage amplifier design
            * Bias voltage driving current and load analysis
            * Required voltages
            * Power supply noise requirements (PSRR Analysis)
            * Power consumption
            * Heat dissipation/Thermal analysis
      * *Video Chain*
         * %RED% Video Chain Schematic Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * All video channels
         * %RED% Video Chain Design Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Preamplifier design and noise analysis
            * ADC buffer amplifier design and noise Analysis
            * Video chain voltage offset noise analysis
            * ADC biasing scheme
            * ADC anti-aliasing filter design
            * ADC communications/digital interface
            * Grounding Scheme (mixed-signal ground plane analysis)
            * Power supply noise analysis (PSRR Analysis and ADC bias analysis)
            * Required voltages
            * Power consumption
            * Heat dissipation/thermal analysis
      * *On-Board Digital Logic*
         * %RED% FPGA Design Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * FPGA block diagram
            * FPGA schematic and pinout
            * FPGA core firmware
            * Multi-board FPGA synchronization
            * Programmability/diagnostic outputs
            * USB communication interface
            * Clock driver interface
            * Waveform generator
            * DAC interface
            * ADC interface
            * Data processing
            * Required voltages
            * Power consumption
            * Heat dissipation/thermal analysis
         * %RED% Communication Design Document %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Communication block diagram
            * Communication schematic
            * USB Communication chipset
            * FPGA/USB interface
            * Communication Traffic Control
            * Fiber optic chipset
            * USB configuration
            * Required voltages
            * Power consumption
            * Het dissipation/thermal analysis
      * *Chassis*
         * %RED% Power Supply Board vs. Chassis Power Supply Trade Study %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Trade off study of power supply board versus power for chassis
            * Voltage/Current Requirements
            * Voltage Noise Requirements
            * Power Dissipation
            * Thermal Analysis/Thermal Management/Active Cooling
            * Connector Pinouts
         * %RED% Backplane %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Full backplane schematic
            * Connector Pinouts
            * Mounting Hardware
            * Test Points
         * %RED% Mechanical %ENDCOLOR% %TWISTY{mode="div" showlink="" hidelink=""
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            * Solidworks drawing of Chassis
            * Mounting points for Chassis
            * Cooling/Temperature Monitoring of Chassis
            * State of Health Monitoring of Chassis

---+++++ Host Software
   * *Communication*
      * %RED% Firmware for USB chipset %ENDCOLOR%
      * %RED% Communication Protocol %ENDCOLOR%
   * *FPGA Code*
      * %RED% FPGA Core Firmware Document %ENDCOLOR%
      * %RED% Firmware Updating/Maintenance %ENDCOLOR%
   * *Waveform Generation*
      * %RED% Waveform Generation Document %ENDCOLOR%
      * %RED% Waveform Creator Software %ENDCOLOR%
      * %RED% Waveform Loader Software %ENDCOLOR%
   * *Host Computer Code*
      * %TWISTY{mode="div" showlink="Command Line Library&nbsp;" hidelink="Command Line Library&nbsp;"
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         * DAC Commands
         * Bias Commands
         * Clock Commands
         * Self-Diagnostics
         * Board Temperature Monitor
         * Exposure Control
         * Shutter Interface
         * Digital Status Bits

---+++++ User Manuals
   * *Observer Use*
      * %RED% GUI Description and Use %ENDCOLOR%
      * %TWISTY{mode="div" showlink="Image File Format Document&nbsp;" hidelink="Image File Format Document&nbsp;"
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         * Header Data
         * Compression Algorithm
         * Interlacing/De-Interlacing Protocol
      * %RED% Quick-Look Image Software %ENDCOLOR%






-- Main.StephenKaye - 02 Jan 2014
   * [[%ATTACHURL%/PreamplifierDesignDocument.doc][PreamplifierDesignDocument.doc]]: Preamplifier Design and Noise Analysis Document