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IFPAC System Documentation
Hardware
Electrical
Single Board Controller
Clock Driver
Clock Driver Schematic (All unique channels)
Clock Driver Design Document
Rail Noise Analysis
Switching Speed Analysis
Driving Current and Load Analysis
Rail Voltage Resolution
Clock Driver Filter Design
Clock Driver Amplifier Design
Power Supply Noise Requirements (PSRR Analysis)
Clock Driver Power Analysis
Power Dissipation
Thermal Analysis
Heat Sink Design (if necessary)
Bias Voltages
Bias Voltages Schematic (All unique channels)
Bias Voltages Design Document
Voltage Noise Analysis
Driving Current and Load Analysis
Bias Voltage Resolution
Bias Filter Design
Bias Voltage Amplifier Design
Power Supply Noise Requirements (PSRR Analysis)
Bias Voltages Power Analysis
Power Dissipation
Thermal Analysis
Heat Sink Design (if necessary)
Analog Signal Chain
Analog Signal Chain Schematic (All unique channels)
Analog Signal Chain Design Document
Signal Chain Amplifier Design
Signal Chain Noise Analysis
Signal Chain Voltage Offset Noise Analysis
Signal Chain Filter Design
ADC Biasing Scheme
ADC Anti-Aliasing Filter
ADC Communications/Digital Interface
Grounding Scheme (mixed-signal ground plane analysis)
Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis)
Analog Signal Chain Power Analysis
Power Dissipation
Thermal Analysis
Heat Sink Design (if necessary)
FPGA
FPGA Schematic and Pinouts
FPGA Design Document
FPGA Core Firmware
FPGA Synchronization
FPGA Programmability/Diagnostic Outputs
USB Communication Interface
ADC Interface
Clock Driver Interface
DAC Interface
FPGA Power Analysis
Power Dissipation
Thermal Analysis
Heat Sink Design (if necessary)
Communications
Communication Hardware Schematic
Communication Design Document
USB Communication Chipset
Fiber Optic Chipset
Communication/FPGA Interface
Communication Traffic Control
Thermal Analysis
Power Dissipation
Heat Sink Design (if necessary)
Single Board Controller
Single Board Controller Complete Schematic
Single Board Controller Power Analysis
SBC Board Power Dissipation
Thermal Analysis/Hotspots
Heat Sink Design (if necessary)
Single Board Controller Design Document
Total numbers of functional blocks (i.e. clocks, biases, signal chains)
Ejector Hardware/Front plate
Test points
Diagnostics/Self-Diagnostics
Backplane connector pinouts
Single Board Controller Layout Document
Functional block placement (clock functions, bias functions, and signal chain)
Ground plane layout and analysis
Power Supply Board
Power Board Schematic
Power Board Design Document
Voltage/Current Requirements
Voltage Noise Requirements
Thermal Analysis
Power Dissipation
Heat Sink/Thermal Management/Active Cooling
Connector Pinouts
Backplane
Backplane Schematic
Backplane Design Document
Connector Pinouts
Mounting Hardware
Test Points
Chassis
Chassis Power Connector
Chassis Power Analysis
Chassis Connector Pinouts
Mechanical
Chassis Design
Solidworks drawing of Chassis
Mounting points for Chassis
Cooling/Temperature Monitoring of Chassis
State of Health Monitoring of Chassis
Software
Communication
Firmware for USB chipset
Communication Protocol
FPGA Code
FPGA Core Firmware Document
Firmware Updating/Maintenance
Waveform Generation
Waveform Generation Document
Waveform Creator Software
Waveform Loader Software
Host Computer Code
Command Line Library
DAC Commands
Bias Commands
Clock Commands
Self-Diagnostics
Board Temperature Monitor
Exposure Control
Shutter Interface
Digital Status Bits
User Manuals
Observer Use
GUI Description and Use
Image File Format Document
Header Data
Compression Algorithm
Interlacing/De-Interlacing Protocol
Quick-Look Image Software
--
StephenKaye
- 02 Jan 2014
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Topic revision: r2 - 2014-01-02
-
StephenKaye
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