IfpacDocumentation < Palomar/ZTF

---+ IFPAC System Documentation

---+++++ Hardware
   * *Electrical*
      * *Single Board Controller*
         * *Clock Driver*
            * %RED% Clock Driver Schematic (All unique channels) %ENDCOLOR%
            * %RED% Clock Driver Design Document %ENDCOLOR%
               * Rail Noise Analysis
               * Switching Speed Analysis
               * Driving Current and Load Analysis
               * Rail Voltage Resolution
               * Clock Driver Filter Design
               * Clock Driver Amplifier Design
               * Power Supply Noise Requirements (PSRR Analysis)
            * %RED% Clock Driver Power Analysis </font>
               * Power Dissipation
               * Thermal Analysis
               * Heat Sink Design (if necessary)
         * *Bias Voltages*
            * %RED% Bias Voltages Schematic (All unique channels) %ENDCOLOR%
            * %RED% Bias Voltages Design Document %ENDCOLOR%
               * Voltage Noise Analysis
               * Driving Current and Load Analysis
               * Bias Voltage Resolution
               * Bias Filter Design
               * Bias Voltage Amplifier Design
               * Power Supply Noise Requirements (PSRR Analysis)
            * %RED% Bias Voltages Power Analysis %ENDCOLOR%
               * Power Dissipation
               * Thermal Analysis
               * Heat Sink Design (if necessary)
         * *Analog Signal Chain*
            * %RED% Analog Signal Chain Schematic (All unique channels) %ENDCOLOR%
            * %RED% Analog Signal Chain Design Document %ENDCOLOR%
               * Signal Chain Amplifier Design
               * Signal Chain Noise Analysis
               * Signal Chain Voltage Offset Noise Analysis
               * Signal Chain Filter Design
               * ADC Biasing Scheme
               * ADC Anti-Aliasing Filter
               * ADC Communications/Digital Interface
               * Grounding Scheme (mixed-signal ground plane analysis)
               * Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis)
            * %RED% Analog Signal Chain Power Analysis %ENDCOLOR%
               * Power Dissipation
               * Thermal Analysis
               * Heat Sink Design (if necessary)
         * *FPGA*
            * %RED% FPGA Schematic and Pinouts %ENDCOLOR%
            * %RED% FPGA Design Document %ENDCOLOR%
               * FPGA Core Firmware
               * FPGA Synchronization
               * FPGA Programmability/Diagnostic Outputs
               * USB Communication Interface
               * ADC Interface
               * Clock Driver Interface
               * DAC Interface
            * %RED% FPGA Power Analysis %ENDCOLOR%
               * Power Dissipation
               * Thermal Analysis
               * Heat Sink Design (if necessary)
         * *Communications*
            * %RED% Communication Hardware Schematic %ENDCOLOR%
            * %RED% Communication Design Document %ENDCOLOR%
               * USB Communication Chipset
               * Fiber Optic Chipset
               * Communication/FPGA Interface
               * Communication Traffic Control
               * Thermal Analysis
               * Power Dissipation
               * Heat Sink Design (if necessary)
         * *Single Board Controller*
            * %RED% Single Board Controller Complete Schematic %ENDCOLOR%     
            * %RED% Single Board Controller Power Analysis %ENDCOLOR%
               * SBC Board Power Dissipation
               * Thermal Analysis/Hotspots
               * Heat Sink Design (if necessary)
            * %RED% Single Board Controller Design Document %ENDCOLOR%
               * Total numbers of functional blocks (i.e. clocks, biases, signal chains)
               * Ejector Hardware/Front plate
               * Test points
               * Diagnostics/Self-Diagnostics
               * Backplane connector pinouts
            * %RED% Single Board Controller Layout Document %ENDCOLOR%
               * Functional block placement (clock functions, bias functions, and signal chain)
               * Ground plane layout and analysis
      * *Power Supply Board*
         * %RED% Power Board Schematic %ENDCOLOR%
         * %RED% Power Board Design Document %ENDCOLOR%
            * Voltage/Current Requirements
            * Voltage Noise Requirements
            * Thermal Analysis
            * Power Dissipation
            * Heat Sink/Thermal Management/Active Cooling
            * Connector Pinouts
      * *Backplane*
         * %RED% Backplane Schematic %ENDCOLOR%
         * %RED% Backplane Design Document %ENDCOLOR%
            * Connector Pinouts
            * Mounting Hardware
            * Test Points
      * *Chassis*
         * %RED% Chassis Power Connector %ENDCOLOR%
            * %RED% Chassis Power Analysis %ENDCOLOR%
         * %RED% Chassis Connector Pinouts %ENDCOLOR%

   * *Mechanical*
      * *Chassis Design*
         * %RED% Solidworks drawing of Chassis %ENDCOLOR%
         * %RED% Mounting points for Chassis %ENDCOLOR%
         * %RED% Cooling/Temperature Monitoring of Chassis %ENDCOLOR%
         * %RED% State of Health Monitoring of Chassis %ENDCOLOR%

---+++++ Software
   * *Communication*
      * %RED% Firmware for USB chipset %ENDCOLOR%
      * %RED% Communication Protocol %ENDCOLOR%
   * *FPGA Code*
      * %RED% FPGA Core Firmware Document %ENDCOLOR%
      * %RED% Firmware Updating/Maintenance %ENDCOLOR%
   * *Waveform Generation*
      * %RED% Waveform Generation Document %ENDCOLOR%
      * %RED% Waveform Creator Software %ENDCOLOR%
      * %RED% Waveform Loader Software %ENDCOLOR%
   * *Host Computer Code*
      * %RED% Command Line Library %ENDCOLOR%
         *  DAC Commands
         * Bias Commands
         * Clock Commands
         * Self-Diagnostics
         * Board Temperature Monitor
         * Exposure Control
         * Shutter Interface
         * Digital Status Bits

---+++++ User Manuals
   * *Observer Use*
      * %RED% GUI Description and Use %ENDCOLOR%
      * %RED% Image File Format Document %ENDCOLOR%
         * Header Data
         * Compression Algorithm
         * Interlacing/De-Interlacing Protocol
      * %RED% Quick-Look Image Software %ENDCOLOR%






-- Main.StephenKaye - 02 Jan 2014
This topic: Palomar/ZTF > WebHome > DetectorReadout > IfpacDocumentation
Topic revision: r2 - 2014-01-02 - StephenKaye