---+ IFPAC System Documentation ---+++++ Hardware * *Electrical* * *Single Board Controller* * *Single Board Controller Overview* * %TWISTY{mode="div" showlink="Single Board Controller Layout Document " hidelink="Single Board Controller Layout Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Functional block placement (clock functions, bias functions, and signal chain) * Ground plane layout and analysis * Configuration Control * Power consumption * Board temperature gradients and thermal analysis * *Clock Driver* * %TWISTY{mode="div" showlink="Clock Driver Schematic " hidelink="Clock Driver Schematic " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * All unique channels * %TWISTY{mode="div" showlink="Clock Driver Design Document " hidelink="Clock Driver Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Rail Noise Analysis * Switching Speed Analysis * Driving Current and Load Analysis * Rail Voltage Resolution * Clock Driver Filter Design * Clock Driver Amplifier Design * Power Supply Noise Requirements (PSRR Analysis) * %TWISTY{mode="div" showlink="Clock Driver Power Analysis " hidelink="Clock Driver Power Analysis " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Power Dissipation * Thermal Analysis * Heat Sink Design (if necessary) * *Bias Voltages* * %TWISTY{mode="div" showlink="Bias Voltage Schematics " hidelink="Bias Voltage Schematics " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * All unique channels * %TWISTY{mode="div" showlink="Bias Voltages Design Document " hidelink="Bias Voltages Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Voltage Noise Analysis * Driving Current and Load Analysis * Bias Voltage Resolution * Bias Filter Design * Bias Voltage Amplifier Design * Power Supply Noise Requirements (PSRR Analysis) * %TWISTY{mode="div" showlink="Bias Voltages Power Analysis " hidelink="Bias Voltages Power Analysis " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Power Dissipation * Thermal Analysis * Heat Sink Design (if necessary) * *Analog Signal Chain* * %TWISTY{mode="div" showlink="Analog Signal Chain Schematics " hidelink="Analog Signal Chain Schematics " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * All unique channels * %TWISTY{mode="div" showlink="Analog Signal Chain Design Document " hidelink="Analog Signal Chain Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Signal Chain Amplifier Design * Signal Chain Noise Analysis * Signal Chain Voltage Offset Noise Analysis * Signal Chain Filter Design * ADC Biasing Scheme * ADC Anti-Aliasing Filter * ADC Communications/Digital Interface * Grounding Scheme (mixed-signal ground plane analysis) * Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis) * %TWISTY{mode="div" showlink="Analog Signal Chain Power Analysis " hidelink="Analog Signal Chain Power Analysis " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Power Dissipation * Thermal Analysis * Heat Sink Design (if necessary) * *FPGA* * %TWISTY{mode="div" showlink="FPGA Schematics " hidelink="FPGA Schematics " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * All unique channels and pinouts * %TWISTY{mode="div" showlink="FPGA Design Document " hidelink="FPGA Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * FPGA Core Firmware * FPGA Synchronization * FPGA Programmability/Diagnostic Outputs * USB Communication Interface * ADC Interface * Clock Driver Interface * DAC Interface * %TWISTY{mode="div" showlink="FPGA Power Analysis " hidelink="FPGA Power Analysis " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Power Dissipation * Thermal Analysis * Heat Sink Design (if necessary) * *Communications* * %TWISTY{mode="div" showlink="Communication Hardware Schematic " hidelink="Communication Hardware Schematic " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Full communication block diagram * Full communication hardware schematic * %TWISTY{mode="div" showlink="Communication Design Document " hidelink="Communication Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * USB Communication Chipset * Fiber Optic Chipset * Communication/FPGA Interface * Communication Traffic Control * Thermal Analysis * Power Dissipation * Heat Sink Design (if necessary) * *Single Board Controller* * %TWISTY{mode="div" showlink="Single Board Controller Complete Schematic " hidelink="Single Board Controller Schematic " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Full schematic with all functional blocks * %TWISTY{mode="div" showlink="Single Board Controller Power Analysis " hidelink="Single Board Controller Power Analysis " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * SBC Board Power Dissipation * Thermal Analysis/Hotspots * Heat Sink Design (if necessary) * %TWISTY{mode="div" showlink="Single Board Controller Design Document " hidelink="Single Board Controller Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Total numbers of functional blocks (i.e. clocks, biases, signal chains) * Ejector Hardware/Front plate * Test points * Diagnostics/Self-Diagnostics * Backplane connector pinouts * *Chassis* * *Power Supply Board vs. Chassis Power Supply Trade Study* * %TWISTY{mode="div" showlink="Power Board Schematic " hidelink="Power Board Schematic " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Trade off study of power supply board versus power for chassis * Board heat transfer and thermal analysis * Water cooling of chassis * %RED% Chassis Power Analysis %ENDCOLOR% * %RED% Chassis Connector Pinouts %ENDCOLOR% * Chassis Power * %TWISTY{mode="div" showlink="Power Board Design Document " hidelink="Power Board Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Voltage/Current Requirements * Voltage Noise Requirements * Thermal Analysis * Power Dissipation * Heat Sink/Thermal Management/Active Cooling * Connector Pinouts * *Backplane* * %TWISTY{mode="div" showlink="Backplane Schematic " hidelink="Backplane Schematic " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Full backplane schematic * %TWISTY{mode="div" showlink="Backplane Design Document " hidelink="Backplane Design Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Connector Pinouts * Mounting Hardware * Test Points * *Mechanical* * *Chassis Design* * %RED% Solidworks drawing of Chassis %ENDCOLOR% * %RED% Mounting points for Chassis %ENDCOLOR% * %RED% Cooling/Temperature Monitoring of Chassis %ENDCOLOR% * %RED% State of Health Monitoring of Chassis %ENDCOLOR% ---+++++ Host Software * *Communication* * %RED% Firmware for USB chipset %ENDCOLOR% * %RED% Communication Protocol %ENDCOLOR% * *FPGA Code* * %RED% FPGA Core Firmware Document %ENDCOLOR% * %RED% Firmware Updating/Maintenance %ENDCOLOR% * *Waveform Generation* * %RED% Waveform Generation Document %ENDCOLOR% * %RED% Waveform Creator Software %ENDCOLOR% * %RED% Waveform Loader Software %ENDCOLOR% * *Host Computer Code* * %TWISTY{mode="div" showlink="Command Line Library " hidelink="Command Line Library " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * DAC Commands * Bias Commands * Clock Commands * Self-Diagnostics * Board Temperature Monitor * Exposure Control * Shutter Interface * Digital Status Bits ---+++++ User Manuals * *Observer Use* * %RED% GUI Description and Use %ENDCOLOR% * %TWISTY{mode="div" showlink="Image File Format Document " hidelink="Image File Format Document " showimgleft="%ICONURLPATH{toggleopen-small}%" hideimgleft="%ICONURLPATH{toggleclose-small}%"}% * Header Data * Compression Algorithm * Interlacing/De-Interlacing Protocol * %RED% Quick-Look Image Software %ENDCOLOR% -- Main.StephenKaye - 02 Jan 2014
This topic: Palomar/ZTF
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Topic revision: r4 - 2014-01-07 - StephenKaye
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