Difference: IfpacDocumentation (1 vs. 17)

Revision 172014-02-06 - RichardDekany

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 184 to 184
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • Software Module Description Document - Empty Document
Deleted:
<
<
      • CCD Control Software
      • Environmental Monitoring Software
      • Power Control Software
      • Filter Control Software
      • Shutter Control Software
      • Focus Control Software
 
      • Supervisory Control Software
Added:
>
>
      • Shutter Control Software
 
      • Temperature Control Software
Deleted:
<
<
      • Data Logging Software
 
      • Vacuum Monitoring Software
Added:
>
>
      • Focus Control Software
      • Power Control Software
      • Filter Control Software
      • Environmental Monitoring Software
      • Data Logging Software
      • CCD Control Software
      • Graphical UI (?)
 
  • Software Inter-Process Communications (IPC) Documents
    <--/twistyPlugin twikiMakeVisibleInline-->

Revision 162014-02-06 - RichardDekany

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META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 183 to 183
 
  • Software Module Descriptions
    <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
    • CCD Control Software - Empty Document
    • Environmental Monitoring Software - Empty Document
    • Power Control Software - Empty Document
    • Filter Control Software - Empty Document
    • Shutter Control Software - Empty Document
    • Focus Control Software - Empty Document
    • Supervisory Control Software - Empty Document
    • Temperature Control Software - Empty Document
    • Data Logging Software - Empty Document
    • Vacuum Monitoring Software - Empty Document
>
>
    • Software Module Description Document - Empty Document
      • CCD Control Software
      • Environmental Monitoring Software
      • Power Control Software
      • Filter Control Software
      • Shutter Control Software
      • Focus Control Software
      • Supervisory Control Software
      • Temperature Control Software
      • Data Logging Software
      • Vacuum Monitoring Software
 
  • Software Inter-Process Communications (IPC) Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
    • CCD Server Main to Client Interface - Empty Document
    • CCD Server Main to CCD Controller API Interface - Empty Document
    • CCD Server Main to CCD Readout Thread Interface - Empty Document
    • CCD Server Main to FITS Header Thread Interface - Empty Document
    • CCD Readout Thread to CCD Controller API Interface - Empty Document
    • CCD Controller API to CCD USB Driver Interface - Empty Document
>
>
    • Software Inter-Process Communicatons (IPC) Document - Empty Document
      • CCD Server Main to Client Interface
      • CCD Server Main to CCD Controller API Interface
      • CCD Server Main to CCD Readout Thread Interface
      • CCD Server Main to FITS Header Thread Interface
      • CCD Readout Thread to CCD Controller API Interface
      • CCD Controller API to CCD USB Driver Interface
 
  • Interfaces to Control Hardware Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
    • Filter Control Software to Filter Controller Interface - Empty Document
    • Focus Control Software to Focus Controller Interface - Empty Document
    • Power Control Software to Power Controller Interface - Empty Document
    • Shutter Control Software to Shutter Controller Interface - Empty Document
    • Temperature Control Software to Termperature Controller Interface - Empty Document
    • Vacuum Monitoring Software to Vacuum Gauge Interface - Empty Document
>
>
    • Control Hardware Interface Control Document
      • Filter Control Software to Filter Controller Interface
      • Focus Control Software to Focus Controller Interface
      • Power Control Software to Power Controller Interface
      • Shutter Control Software to Shutter Controller Interface
      • Temperature Control Software to Temperature Controller Interface
      • Vacuum Monitoring Software to Vacuum Gauge Interface
 
  • FITS File Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
Line: 221 to 224
 
      • When keywords are collected from sources
      • When is the header written
      • When and how are the pixel data written
Changed:
<
<
    • TCS to FITS Header Thread Interface - Empty Document
    • Filter Control Software to FITS Header Thread Interface - Empty Document
    • Shutter Control Software to FITS Header Thread Interface - Empty Document
    • Focus Control Software to FITS Header Thread Interface - Empty Document
    • Environmental Monitor Software to FITS Header Thread Interface - Empty Document
    • Temperature Control Software to FITS Header Thread Interface - Empty Document
>
>
      • TCS to FITS Header Thread Interface
      • Filter Control Software to FITS Header Thread Interface
      • Shutter Control Software to FITS Header Thread Interface
      • Focus Control Software to FITS Header Thread Interface
      • Environmental Monitor Software to FITS Header Thread Interface
      • Temperature Control Software to FITS Header Thread Interface
 
Software Tools

Revision 152014-02-05 - RichardDekany

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 233 to 233
 
  • Waveform Generation
    <--/twistyPlugin twikiMakeVisibleInline-->
Added:
>
>
    • Waveform Creator Software Documentation - Empty Document
 
    • Waveform Creator Software - Empty Document
      • Waveform commands
      • Waveform output bit assignments

Revision 142014-01-15 - StephenKaye

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META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


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 hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • Waveform Creator Software - Empty Document
      • Waveform commands
Changed:
<
<
      • Waveform output bit assignments %ENDCOLOR
>
>
      • Waveform output bit assignments
 
      • How to define waveforms
      • Waveform display software
      • How to load waveforms to single board controller
Line: 250 to 250
 
META FILEATTACHMENT attachment="VideoPostProcessorDesignDocument.docx" attr="" comment="ADC Buffer Design and Noise Analysis" date="1389393746" name="VideoPostProcessorDesignDocument.docx" path="VideoPostProcessorDesignDocument.docx" size="151640" stream="VideoPostProcessorDesignDocument.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="Anti-AliasingFilterDesign.docx" attr="" comment="Anti-Aliasing Filter Design and Motivation" date="1389394133" name="Anti-AliasingFilterDesign.docx" path="Anti-AliasingFilterDesign.docx" size="737866" stream="Anti-AliasingFilterDesign.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="ADCBufferSchematic.pdf" attr="" comment="ADC Buffer Schematic" date="1389397308" name="ADCBufferSchematic.pdf" path="ADCBufferSchematic.pdf" size="36455" stream="ADCBufferSchematic.pdf" user="Main.StephenKaye" version="1"
Changed:
<
<
META FILEATTACHMENT attachment="ZTFDesignDocumentTemplate.docx" attr="" comment="Design Document Template" date="1389644318" name="ZTFDesignDocumentTemplate.docx" path="ZTFDesignDocumentTemplate.docx" size="22826" stream="ZTFDesignDocumentTemplate.docx" user="Main.StephenKaye" version="1"
>
>
META FILEATTACHMENT attachment="ZTFDesignDocumentTemplate.docx" attr="" comment="Design Document Template" date="1389821890" name="ZTFDesignDocumentTemplate.docx" path="ZTFDesignDocumentTemplate.docx" size="23744" stream="ZTFDesignDocumentTemplate.docx" user="Main.StephenKaye" version="2"

Revision 132014-01-15 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 141 to 141
 
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
Added:
>
>
Firmware
  • Communication Firmware Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
    • Firmware for USB chipset - Empty Document
      • USB Protocol
      • Bit rate control
      • Communication protocol
      • Control/Handshaking protocol and signals
  • FPGA Code
    <--/twistyPlugin twikiMakeVisibleInline-->
    • FPGA Core Firmware Document - Empty Document
      • Compiling FPGA Firmware
      • JTAG interface for FPGA
      • EEPROM
      • Firmware code verification
      • Firmware Updating/Maintenance
 
Host Software
Changed:
<
<
  • Review Documents %TWISTY{mode="div" showlink="" hidelink=""
>
>
  • Review Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • Software Requirements Document - Empty Document
Line: 161 to 180
 
      • Shutdown procedure description
      • List of operations and how they are used
    • System Command Summary - Empty Document
Changed:
<
<
  • Software Module Descriptions %TWISTY{mode="div" showlink="" hidelink=""
>
>
  • Software Module Descriptions %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • CCD Control Software - Empty Document
Line: 174 to 193
 
    • Temperature Control Software - Empty Document
    • Data Logging Software - Empty Document
    • Vacuum Monitoring Software - Empty Document
Changed:
<
<
  • Software Inter-Process Communications (IPC) Documents %TWISTY{mode="div" showlink="" hidelink=""
>
>
  • Software Inter-Process Communications (IPC) Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • CCD Server Main to Client Interface - Empty Document
Line: 183 to 202
 
    • CCD Server Main to FITS Header Thread Interface - Empty Document
    • CCD Readout Thread to CCD Controller API Interface - Empty Document
    • CCD Controller API to CCD USB Driver Interface - Empty Document
Changed:
<
<
  • Interfaces to Control Hardware Documents %TWISTY{mode="div" showlink="" hidelink=""
>
>
  • Interfaces to Control Hardware Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • Filter Control Software to Filter Controller Interface - Empty Document
Line: 192 to 211
 
    • Shutter Control Software to Shutter Controller Interface - Empty Document
    • Temperature Control Software to Termperature Controller Interface - Empty Document
    • Vacuum Monitoring Software to Vacuum Gauge Interface - Empty Document
Changed:
<
<
  • FITS File Documents %TWISTY{mode="div" showlink="" hidelink=""
>
>
  • FITS File Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
    • FITS File Document - Empty Document
Line: 209 to 228
 
    • Environmental Monitor Software to FITS Header Thread Interface - Empty Document
    • Temperature Control Software to FITS Header Thread Interface - Empty Document

Added:
>
>
Software Tools
 
Changed:
<
<
  • Communication
    • Firmware for USB chipset
    • Communication Protocol
  • FPGA Code
    • FPGA Core Firmware Document
    • Firmware Updating/Maintenance
  • Waveform Generation
    • Waveform Generation Document
    • Waveform Creator Software
    • Waveform Loader Software
  • Host Computer Code
    • <--/twistyPlugin twikiMakeVisibleInline-->
      • DAC Commands
      • Bias Commands
      • Clock Commands
      • Self-Diagnostics
      • Board Temperature Monitor
      • Exposure Control
      • Shutter Interface
      • Digital Status Bits

User Manuals
>
>
  • Waveform Generation
    <--/twistyPlugin twikiMakeVisibleInline-->
    • Waveform Creator Software - Empty Document
      • Waveform commands
      • Waveform output bit assignments %ENDCOLOR
      • How to define waveforms
      • Waveform display software
      • How to load waveforms to single board controller
 

Revision 122014-01-14 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 141 to 141
 
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
Changed:
<
<
Software
>
>
Host Software
 
  • Review Documents
    <--/twistyPlugin twikiMakeVisibleInline-->

Revision 112014-01-14 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 141 to 141
 
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
Changed:
<
<
Host Software
>
>
Software
  • Review Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
    • Software Requirements Document - Empty Document
      • Descriptions of system requirements
      • Descriptions of functional requirements
    • Software Architecture Document - Empty Document
      • Description of the overall layout of the software
      • Instrument context diagram
      • List and descriptions of software units
      • List and descriptions of interfaces between units
      • List and descriptions of interfaces between software and hardware
    • Preliminary Design Review Document - Empty Document
    • Detailed Design Review Document - Empty Document
    • Instrument Users Manual - Empty Document
      • Startup procedure description
      • Shutdown procedure description
      • List of operations and how they are used
    • System Command Summary - Empty Document
  • Software Module Descriptions
    <--/twistyPlugin twikiMakeVisibleInline-->
    • CCD Control Software - Empty Document
    • Environmental Monitoring Software - Empty Document
    • Power Control Software - Empty Document
    • Filter Control Software - Empty Document
    • Shutter Control Software - Empty Document
    • Focus Control Software - Empty Document
    • Supervisory Control Software - Empty Document
    • Temperature Control Software - Empty Document
    • Data Logging Software - Empty Document
    • Vacuum Monitoring Software - Empty Document
  • Software Inter-Process Communications (IPC) Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
    • CCD Server Main to Client Interface - Empty Document
    • CCD Server Main to CCD Controller API Interface - Empty Document
    • CCD Server Main to CCD Readout Thread Interface - Empty Document
    • CCD Server Main to FITS Header Thread Interface - Empty Document
    • CCD Readout Thread to CCD Controller API Interface - Empty Document
    • CCD Controller API to CCD USB Driver Interface - Empty Document
  • Interfaces to Control Hardware Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
    • Filter Control Software to Filter Controller Interface - Empty Document
    • Focus Control Software to Focus Controller Interface - Empty Document
    • Power Control Software to Power Controller Interface - Empty Document
    • Shutter Control Software to Shutter Controller Interface - Empty Document
    • Temperature Control Software to Termperature Controller Interface - Empty Document
    • Vacuum Monitoring Software to Vacuum Gauge Interface - Empty Document
  • FITS File Documents
    <--/twistyPlugin twikiMakeVisibleInline-->
    • FITS File Document - Empty Document
      • List of header keywords
      • Sources for keyword values
      • How keywords are collected from sources
      • When keywords are collected from sources
      • When is the header written
      • When and how are the pixel data written
    • TCS to FITS Header Thread Interface - Empty Document
    • Filter Control Software to FITS Header Thread Interface - Empty Document
    • Shutter Control Software to FITS Header Thread Interface - Empty Document
    • Focus Control Software to FITS Header Thread Interface - Empty Document
    • Environmental Monitor Software to FITS Header Thread Interface - Empty Document
    • Temperature Control Software to FITS Header Thread Interface - Empty Document

 
  • Communication
    • Firmware for USB chipset
    • Communication Protocol

Revision 102014-01-14 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 15 to 15
 
      • Single Board Controller Layout Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
        • Functional block placement (clock functions, bias functions, and signal chain) - Empty Document
        • Ground plane layout and analysis - Empty Document
        • Configuration Control - Empty Document
        • Power consumption - Empty Document
        • Board temperature gradients and thermal analysis - Empty Document
>
>
        • Single Board Controller Layout Document - Empty Document
          • Functional block placement (clock functions, bias functions, and signal chain)
          • Ground plane layout and analysis
          • Configuration Control
          • Power consumption
          • Board temperature gradients and thermal analysis
 
    • Clock Driver
      • Clock Driver Schematic Documents %TWISTY{mode="div" showlink="" hidelink=""
showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif"
Line: 61 to 62
 
      • Video Chain Schematic Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
        • Preamplifier Schematic
>
>
        • Preamplifier Schematic - Empty Document
 
Changed:
<
<
          • Grounding Scheme (mixed-signal ground plane analysis)
>
>
          • Grounding Scheme
 
          • Power supply noise analysis (PSRR Analysis and ADC bias analysis)
          • Required voltages
          • Power consumption
Line: 77 to 78
 
          • ADC communications/digital interface
          • Video chain voltage offset noise analysis
          • ADC biasing scheme
Changed:
<
<
          • Grounding Scheme (mixed-signal ground plane analysis)
>
>
          • Grounding Scheme
 
          • Power supply noise analysis (PSRR Analysis and ADC bias analysis)
          • Required voltages
          • Power consumption
Line: 86 to 87
 
      • FPGA Design Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Added:
>
>
        • FPGA Design Document - Empty Document
 
        • FPGA block diagram
        • FPGA schematic and pinout
        • FPGA core firmware
Line: 103 to 105
 
      • Communication Design Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Added:
>
>
        • Communication Design Document - Empty Document
 
        • Communication block diagram
        • Communication schematic
        • USB Communication chipset
Line: 164 to 167
 
User Manuals
  • Observer Use
Deleted:
<
<
    • GUI Description and Use
 
Deleted:
<
<
    • Quick-Look Image Software
 

Revision 92014-01-13 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 7 to 7
  Yellow - Document in progress
Green - Document completed
Added:
>
>
ZTFDesignDocumentTemplate - Use this template for design documents
 
Hardware
  • Single Board Controller
    • Single Board Controller Overview
      • Single Board Controller Layout Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
        • Functional block placement (clock functions, bias functions, and signal chain)
        • Ground plane layout and analysis
        • Configuration Control
        • Power consumption
        • Board temperature gradients and thermal analysis
>
>
        • Functional block placement (clock functions, bias functions, and signal chain) - Empty Document
        • Ground plane layout and analysis - Empty Document
        • Configuration Control - Empty Document
        • Power consumption - Empty Document
        • Board temperature gradients and thermal analysis - Empty Document
 
    • Clock Driver
      • Clock Driver Schematic Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
        • All clock channels
>
>
        • All clock channels - Empty Document
 
      • Clock Driver Design Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Added:
>
>
        • Clock Design and Noise Analysis - Empty Document
 
        • Clock voltage range
        • Clock voltage resolution
        • Clock voltage noise analysis
Changed:
<
<
        • Switching speed analysis
        • Clock driver amplifier design
        • Driving current and load analysis
>
>
          • Clock voltage amplifier design
          • Clock driving current and load analysis
          • Clock switching speed
 
        • Required voltages
Changed:
<
<
        • Power Supply Noise Requirements (PSRR Analysis)
>
>
          • Power supply noise requirements (PSRR Analysis)
 
        • Power consumption
Deleted:
<
<
        • Thermal Analysis
 
        • Heat dissipation/Thermal analysis
    • Bias Voltages
      • Bias Voltage Schematic Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Changed:
<
<
        • All bias channels
>
>
        • All bias channels - Empty Document
 
      • Bias Voltage Design Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
Added:
>
>
        • Bias Design and Noise Analysis - Empty Document
 
        • Bias voltage range
        • Bias voltage resolution
        • Bias voltage noise analysis
Line: 59 to 62
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
        • Preamplifier Schematic
Changed:
<
<
>
>
 
Changed:
<
<
>
>
 
        • ADC communications/digital interface
Added:
>
>
          • Video chain voltage offset noise analysis
          • ADC biasing scheme
 
        • Grounding Scheme (mixed-signal ground plane analysis)
        • Power supply noise analysis (PSRR Analysis and ADC bias analysis)
        • Required voltages
Line: 176 to 184
 
META FILEATTACHMENT attachment="VideoPostProcessorDesignDocument.docx" attr="" comment="ADC Buffer Design and Noise Analysis" date="1389393746" name="VideoPostProcessorDesignDocument.docx" path="VideoPostProcessorDesignDocument.docx" size="151640" stream="VideoPostProcessorDesignDocument.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="Anti-AliasingFilterDesign.docx" attr="" comment="Anti-Aliasing Filter Design and Motivation" date="1389394133" name="Anti-AliasingFilterDesign.docx" path="Anti-AliasingFilterDesign.docx" size="737866" stream="Anti-AliasingFilterDesign.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="ADCBufferSchematic.pdf" attr="" comment="ADC Buffer Schematic" date="1389397308" name="ADCBufferSchematic.pdf" path="ADCBufferSchematic.pdf" size="36455" stream="ADCBufferSchematic.pdf" user="Main.StephenKaye" version="1"
Added:
>
>
META FILEATTACHMENT attachment="ZTFDesignDocumentTemplate.docx" attr="" comment="Design Document Template" date="1389644318" name="ZTFDesignDocumentTemplate.docx" path="ZTFDesignDocumentTemplate.docx" size="22826" stream="ZTFDesignDocumentTemplate.docx" user="Main.StephenKaye" version="1"

Revision 82014-01-10 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation


Line: 10 to 10
 
Hardware
  • Single Board Controller
    • Single Board Controller Overview
Changed:
<
<
      • Single Board Controller Layout Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • Single Board Controller Layout Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Functional block placement (clock functions, bias functions, and signal chain)
        • Ground plane layout and analysis
        • Configuration Control
        • Power consumption
        • Board temperature gradients and thermal analysis
>
>
        • Functional block placement (clock functions, bias functions, and signal chain)
        • Ground plane layout and analysis
        • Configuration Control
        • Power consumption
        • Board temperature gradients and thermal analysis
 
    • Clock Driver
Changed:
<
<
      • Clock Driver Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • Clock Driver Schematic Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • All clock channels
      • Clock Driver Design Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
        • All clock channels
      • Clock Driver Design Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Clock voltage range
        • Clock voltage resolution
        • Clock voltage noise analysis
        • Switching speed analysis
        • Clock driver amplifier design
        • Driving current and load analysis
        • Required voltages
        • Power Supply Noise Requirements (PSRR Analysis)
        • Power consumption
        • Thermal Analysis
        • Heat dissipation/Thermal analysis
>
>
        • Clock voltage range
        • Clock voltage resolution
        • Clock voltage noise analysis
        • Switching speed analysis
        • Clock driver amplifier design
        • Driving current and load analysis
        • Required voltages
        • Power Supply Noise Requirements (PSRR Analysis)
        • Power consumption
        • Thermal Analysis
        • Heat dissipation/Thermal analysis
 
    • Bias Voltages
Changed:
<
<
      • Bias Voltage Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • Bias Voltage Schematic Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • All bias channels
      • Bias Voltage Design Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
        • All bias channels
      • Bias Voltage Design Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Bias voltage range
        • Bias voltage resolution
        • Bias voltage noise analysis
        • Bias voltage amplifier design
        • Bias voltage driving current and load analysis
        • Required voltages
        • Power supply noise requirements (PSRR Analysis)
        • Power consumption
        • Heat dissipation/Thermal analysis
>
>
        • Bias voltage range
        • Bias voltage resolution
        • Bias voltage noise analysis
        • Bias voltage amplifier design
        • Bias voltage driving current and load analysis
        • Required voltages
        • Power supply noise requirements (PSRR Analysis)
        • Power consumption
        • Heat dissipation/Thermal analysis
 
    • Video Chain
Changed:
<
<
      • Video Chain Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • Video Chain Schematic Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • All video channels
      • Video Chain Design Document
        <--/twistyPlugin twikiMakeVisibleInline-->
        • Preamplifier design and noise analysis
        • ADC buffer amplifier design and noise Analysis
        • Video chain voltage offset noise analysis
        • ADC biasing scheme
        • ADC anti-aliasing filter design
        • ADC communications/digital interface
        • Grounding Scheme (mixed-signal ground plane analysis)
        • Power supply noise analysis (PSRR Analysis and ADC bias analysis)
        • Required voltages
        • Power consumption
        • Heat dissipation/thermal analysis
>
>
 
    • On-Board Digital Logic
Changed:
<
<
      • FPGA Design Document %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • FPGA Design Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • FPGA block diagram
        • FPGA schematic and pinout
        • FPGA core firmware
        • Multi-board FPGA synchronization
        • Programmability/diagnostic outputs
        • USB communication interface
        • Clock driver interface
        • Waveform generator
        • DAC interface
        • ADC interface
        • Data processing
        • Required voltages
        • Power consumption
        • Heat dissipation/thermal analysis
      • Communication Design Document
        <--/twistyPlugin twikiMakeVisibleInline-->
        • Communication block diagram
        • Communication schematic
        • USB Communication chipset
        • FPGA/USB interface
        • Communication Traffic Control
        • Fiber optic chipset
        • USB configuration
        • Required voltages
        • Power consumption
        • Het dissipation/thermal analysis
>
>
        • FPGA block diagram
        • FPGA schematic and pinout
        • FPGA core firmware
        • Multi-board FPGA synchronization
        • Programmability/diagnostic outputs
        • USB communication interface
        • Clock driver interface
        • Waveform generator
        • DAC interface
        • ADC interface
        • Data processing
        • Required voltages
        • Power consumption
        • Heat dissipation/thermal analysis
      • Communication Design Documents
        <--/twistyPlugin twikiMakeVisibleInline-->
        • Communication block diagram
        • Communication schematic
        • USB Communication chipset
        • FPGA/USB interface
        • Communication Traffic Control
        • Fiber optic chipset
        • USB configuration
        • Required voltages
        • Power consumption
        • Heat dissipation/thermal analysis
 
    • Chassis
Changed:
<
<
      • Power Supply Board vs. Chassis Power Supply Trade Study %TWISTY{mode="div" showlink="" hidelink=""
>
>
      • Power Supply Board vs. Chassis Power Supply Trade Study %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Trade off study of power supply board versus power for chassis
        • Voltage/Current Requirements
        • Voltage Noise Requirements
        • Power Dissipation
        • Thermal Analysis/Thermal Management/Active Cooling
        • Connector Pinouts
      • Backplane %TWISTY{mode="div" showlink="" hidelink=""
>
>
        • Trade off study of power supply board versus power for chassis
        • Voltage/Current Requirements
        • Voltage Noise Requirements
        • Power Dissipation
        • Thermal Analysis/Thermal Management/Active Cooling
        • Connector Pinouts
      • Backplane Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Full backplane schematic
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
      • Mechanical %TWISTY{mode="div" showlink="" hidelink=""
>
>
        • Full backplane schematic
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
      • Mechanical Documents %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Solidworks drawing of Chassis
        • Mounting points for Chassis
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
>
>
        • Solidworks drawing of Chassis
        • Mounting points for Chassis
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
 
Host Software
  • Communication
Line: 170 to 171
 

-- StephenKaye - 02 Jan 2014

Deleted:
<
<
 
META FILEATTACHMENT attachment="PreamplifierDesignDocument.doc" attr="" comment="Preamplifier Design and Noise Analysis Document" date="1389227040" name="PreamplifierDesignDocument.doc" path="PreamplifierDesignDocument.doc" size="1287168" stream="PreamplifierDesignDocument.doc" user="Main.StephenKaye" version="1"
Added:
>
>
META FILEATTACHMENT attachment="VideoPostProcessorDesignDocument.docx" attr="" comment="ADC Buffer Design and Noise Analysis" date="1389393746" name="VideoPostProcessorDesignDocument.docx" path="VideoPostProcessorDesignDocument.docx" size="151640" stream="VideoPostProcessorDesignDocument.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="Anti-AliasingFilterDesign.docx" attr="" comment="Anti-Aliasing Filter Design and Motivation" date="1389394133" name="Anti-AliasingFilterDesign.docx" path="Anti-AliasingFilterDesign.docx" size="737866" stream="Anti-AliasingFilterDesign.docx" user="Main.StephenKaye" version="1"
META FILEATTACHMENT attachment="ADCBufferSchematic.pdf" attr="" comment="ADC Buffer Schematic" date="1389397308" name="ADCBufferSchematic.pdf" path="ADCBufferSchematic.pdf" size="36455" stream="ADCBufferSchematic.pdf" user="Main.StephenKaye" version="1"

Revision 72014-01-09 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Added:
>
>

Legend:
Red - Document empty
Yellow - Document in progress
Green - Document completed
 
Hardware
Deleted:
<
<
  • Electrical
 
    • Single Board Controller
      • Single Board Controller Overview
Changed:
<
<
        • %TWISTY{mode="div" showlink="Single Board Controller Layout Document " hidelink="Single Board Controller Layout Document "
>
>
      • Single Board Controller Layout Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • Functional block placement (clock functions, bias functions, and signal chain)
Line: 15 to 19
 
          • Power consumption
          • Board temperature gradients and thermal analysis
      • Clock Driver
Changed:
<
<
        • %TWISTY{mode="div" showlink="Clock Driver Schematic Document " hidelink="Clock Driver Schematic Document "
>
>
      • Clock Driver Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • All clock channels
Changed:
<
<
        • %TWISTY{mode="div" showlink="Clock Driver Design Document " hidelink="Clock Driver Design Document "
>
>
      • Clock Driver Design Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • Clock voltage range
Line: 34 to 38
 
          • Thermal Analysis
          • Heat dissipation/Thermal analysis
      • Bias Voltages
Changed:
<
<
        • %TWISTY{mode="div" showlink="Bias Voltage Schematic Document " hidelink="Bias Voltage Schematic Document "
>
>
      • Bias Voltage Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • All bias channels
Changed:
<
<
        • %TWISTY{mode="div" showlink="Bias Voltage Design Document " hidelink="Bias Voltage Design Document "
>
>
      • Bias Voltage Design Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • Bias voltage range
Line: 51 to 55
 
          • Power consumption
          • Heat dissipation/Thermal analysis
      • Video Chain
Changed:
<
<
        • %TWISTY{mode="div" showlink="Video Chain Schematic Document " hidelink="Video Chain Schematic Document "
>
>
      • Video Chain Schematic Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • All video channels
Changed:
<
<
        • %TWISTY{mode="div" showlink="Video Chain Design Document " hidelink="Analog Signal Chain Design Document "
>
>
      • Video Chain Design Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • Preamplifier design and noise analysis
Line: 70 to 74
 
          • Power consumption
          • Heat dissipation/thermal analysis
      • On-Board Digital Logic
Changed:
<
<
        • %TWISTY{mode="div" showlink="FPGA Design Document " hidelink="FPGA Design Document "
>
>
      • FPGA Design Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • FPGA block diagram
Line: 87 to 91
 
          • Required voltages
          • Power consumption
          • Heat dissipation/thermal analysis
Changed:
<
<
      • %TWISTY{mode="div" showlink="Communication Design Document " hidelink="Communication Design Document "
>
>
      • Communication Design Document %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
        • Communication block diagram
Line: 101 to 105
 
        • Power consumption
        • Het dissipation/thermal analysis
    • Chassis
Changed:
<
<
      • %TWISTY{mode="div" showlink="Power Supply Board vs. Chassis Power Supply Trade Study " hidelink="Power Supply Board vs. Chassis Power Supply Trade Study "
>
>
      • Power Supply Board vs. Chassis Power Supply Trade Study %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
        • Trade off study of power supply board versus power for chassis
Line: 110 to 114
 
        • Power Dissipation
        • Thermal Analysis/Thermal Management/Active Cooling
        • Connector Pinouts
Changed:
<
<
      • %TWISTY{mode="div" showlink="Backplane " hidelink="Backplane "
>
>
      • Backplane %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
        • Full backplane schematic
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
Changed:
<
<
      • %TWISTY{mode="div" showlink="Mechanical " hidelink="Machanical "
>
>
      • Mechanical %TWISTY{mode="div" showlink="" hidelink=""
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
        • Solidworks drawing of Chassis
        • Mounting points for Chassis
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
>
>
        • Solidworks drawing of Chassis
        • Mounting points for Chassis
        • Cooling/Temperature Monitoring of Chassis
        • State of Health Monitoring of Chassis
 
Host Software
  • Communication
Line: 166 to 170
 

-- StephenKaye - 02 Jan 2014

Added:
>
>

META FILEATTACHMENT attachment="PreamplifierDesignDocument.doc" attr="" comment="Preamplifier Design and Noise Analysis Document" date="1389227040" name="PreamplifierDesignDocument.doc" path="PreamplifierDesignDocument.doc" size="1287168" stream="PreamplifierDesignDocument.doc" user="Main.StephenKaye" version="1"

Revision 62014-01-08 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Line: 15 to 15
 
          • Power consumption
          • Board temperature gradients and thermal analysis
      • Clock Driver
Changed:
<
<
        • %TWISTY{mode="div" showlink="Clock Driver Schematic " hidelink="Clock Driver Schematic "
>
>
        • %TWISTY{mode="div" showlink="Clock Driver Schematic Document " hidelink="Clock Driver Schematic Document "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
          • Rail Noise Analysis
          • Switching Speed Analysis
          • Driving Current and Load Analysis
          • Rail Voltage Resolution
          • Clock Driver Filter Design
          • Clock Driver Amplifier Design
>
>
          • Clock voltage range
          • Clock voltage resolution
          • Clock voltage noise analysis
          • Switching speed analysis
          • Clock driver amplifier design
          • Driving current and load analysis
          • Required voltages
 
          • Power Supply Noise Requirements (PSRR Analysis)
Changed:
<
<
>
>
          • Power consumption
 
          • Thermal Analysis
Changed:
<
<
          • Heat Sink Design (if necessary)
>
>
          • Heat dissipation/Thermal analysis
 
      • Bias Voltages
Changed:
<
<
        • %TWISTY{mode="div" showlink="Bias Voltage Schematics " hidelink="Bias Voltage Schematics "
>
>
        • %TWISTY{mode="div" showlink="Bias Voltage Schematic Document " hidelink="Bias Voltage Schematic Document "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • All bias channels
Changed:
<
<
        • <--/twistyPlugin twikiMakeVisibleInline-->
          • Voltage Noise Analysis
          • Driving Current and Load Analysis
          • Bias Voltage Resolution
          • Bias Filter Design
          • Bias Voltage Amplifier Design
          • Power Supply Noise Requirements (PSRR Analysis)
        • %TWISTY{mode="div" showlink="Bias Voltages Power Analysis " hidelink="Bias Voltages Power Analysis "
>
>
        • %TWISTY{mode="div" showlink="Bias Voltage Design Document " hidelink="Bias Voltage Design Document "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
>
>
          • Bias voltage range
          • Bias voltage resolution
          • Bias voltage noise analysis
          • Bias voltage amplifier design
          • Bias voltage driving current and load analysis
          • Required voltages
          • Power supply noise requirements (PSRR Analysis)
          • Power consumption
          • Heat dissipation/Thermal analysis
 
      • Video Chain
Changed:
<
<
        • %TWISTY{mode="div" showlink="Video Chain Schematics " hidelink="Video Chain Schematics "
>
>
        • %TWISTY{mode="div" showlink="Video Chain Schematic Document " hidelink="Video Chain Schematic Document "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
          • Preamplifier Design and Noise Analysis
          • ADC Buffer Amplifier Design and Noise Analysis
          • Video Chain Voltage Offset Noise Analysis
          • ADC Biasing Scheme
          • ADC Anti-Aliasing Filter Design
          • ADC Communications/Digital Interface
>
>
          • Preamplifier design and noise analysis
          • ADC buffer amplifier design and noise Analysis
          • Video chain voltage offset noise analysis
          • ADC biasing scheme
          • ADC anti-aliasing filter design
          • ADC communications/digital interface
 
          • Grounding Scheme (mixed-signal ground plane analysis)
Changed:
<
<
>
>
          • Power supply noise analysis (PSRR Analysis and ADC bias analysis)
          • Required voltages
          • Power consumption
          • Heat dissipation/thermal analysis
 
Changed:
<
<
          • FPGA schematic and pinouts
          • FPGA Block Diagram
          • FPGA Core Firmware
          • FPGA Synchronization
          • FPGA Programmability/Diagnostic Outputs
          • USB Communication Interface
          • ADC Interface
          • Clock Driver Interface
          • DAC Interface
          • Power Dissipation and Thermal Analysis
          • Data Processing
        • Waveform Generation
          • Timing Generator
          • Waveform Generation Creator Software
      • Communications
>
>
          • FPGA block diagram
          • FPGA schematic and pinout
          • FPGA core firmware
          • Multi-board FPGA synchronization
          • Programmability/diagnostic outputs
          • USB communication interface
          • Clock driver interface
          • Waveform generator
          • DAC interface
          • ADC interface
          • Data processing
          • Required voltages
          • Power consumption
          • Heat dissipation/thermal analysis
 
Changed:
<
<
          • USB Communication Chipset
          • Fiber Optic Chipset
          • Communication/FPGA Interface
>
>
        • Communication block diagram
        • Communication schematic
        • USB Communication chipset
        • FPGA/USB interface
 
          • Communication Traffic Control
Changed:
<
<
>
>
        • Fiber optic chipset
        • USB configuration
        • Required voltages
        • Power consumption
        • Het dissipation/thermal analysis
 
    • Chassis
      • %TWISTY{mode="div" showlink="Power Supply Board vs. Chassis Power Supply Trade Study " hidelink="Power Supply Board vs. Chassis Power Supply Trade Study "
showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif"

Revision 52014-01-07 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Line: 18 to 18
 
Changed:
<
<
          • All unique channels
>
>
          • All clock channels
 
Line: 39 to 39
 
Changed:
<
<
          • All unique channels
>
>
          • All bias channels
 
Line: 55 to 55
 
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
Changed:
<
<
      • Analog Signal Chain
        • %TWISTY{mode="div" showlink="Analog Signal Chain Schematics " hidelink="Analog Signal Chain Schematics "
>
>
      • Video Chain
        • %TWISTY{mode="div" showlink="Video Chain Schematics " hidelink="Video Chain Schematics "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
          • All unique channels
        • %TWISTY{mode="div" showlink="Analog Signal Chain Design Document " hidelink="Analog Signal Chain Design Document "
>
>
          • All video channels
        • %TWISTY{mode="div" showlink="Video Chain Design Document " hidelink="Analog Signal Chain Design Document "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
Changed:
<
<
          • Signal Chain Amplifier Design
          • Signal Chain Noise Analysis
          • Signal Chain Voltage Offset Noise Analysis
          • Signal Chain Filter Design
>
>
          • Preamplifier Design and Noise Analysis
          • ADC Buffer Amplifier Design and Noise Analysis
          • Video Chain Voltage Offset Noise Analysis
 
          • ADC Biasing Scheme
Changed:
<
<
          • ADC Anti-Aliasing Filter
>
>
          • ADC Anti-Aliasing Filter Design
 
          • ADC Communications/Digital Interface
          • Grounding Scheme (mixed-signal ground plane analysis)
          • Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis)
Changed:
<
<
        • %TWISTY{mode="div" showlink="Analog Signal Chain Power Analysis " hidelink="Analog Signal Chain Power Analysis "
>
>
        • %TWISTY{mode="div" showlink="Video Chain Power Analysis " hidelink="Video Chain Power Analysis "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
Changed:
<
<
>
>
      • On-Board Digital Logic
 
Added:
>
>
          • FPGA schematic and pinouts
          • FPGA Block Diagram
 
          • FPGA Core Firmware
          • FPGA Synchronization
          • FPGA Programmability/Diagnostic Outputs
Line: 93 to 90
 
          • ADC Interface
          • Clock Driver Interface
          • DAC Interface
Changed:
<
<
>
>
          • Power Dissipation and Thermal Analysis
          • Data Processing
        • Waveform Generation
          • Timing Generator
          • Waveform Generation Creator Software
 
      • Communications
        • %TWISTY{mode="div" showlink="Communication Hardware Schematic " hidelink="Communication Hardware Schematic "
showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif"
Line: 135 to 131
 
          • Diagnostics/Self-Diagnostics
          • Backplane connector pinouts
    • Chassis
Changed:
<
<
      • Power Supply Board vs. Chassis Power Supply Trade Study
      • %TWISTY{mode="div" showlink="Power Board Schematic " hidelink="Power Board Schematic "
>
>
      • %TWISTY{mode="div" showlink="Power Supply Board vs. Chassis Power Supply Trade Study " hidelink="Power Supply Board vs. Chassis Power Supply Trade Study "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
        • Trade off study of power supply board versus power for chassis
Deleted:
<
<
 
        • Voltage/Current Requirements
        • Voltage Noise Requirements
Deleted:
<
<
        • Thermal Analysis
 
        • Power Dissipation
Changed:
<
<
        • Heat Sink/Thermal Management/Active Cooling
>
>
        • Thermal Analysis/Thermal Management/Active Cooling
 
        • Connector Pinouts
Changed:
<
<
      • Backplane
        • %TWISTY{mode="div" showlink="Backplane Schematic " hidelink="Backplane Schematic "
>
>
      • %TWISTY{mode="div" showlink="Backplane " hidelink="Backplane "
 showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif" hideimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleclose-small.gif"}%
            • Full backplane schematic
Deleted:
<
<
 
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
Changed:
<
<
  • Mechanical
    • Chassis Design
>
>
 
      • Solidworks drawing of Chassis
      • Mounting points for Chassis
      • Cooling/Temperature Monitoring of Chassis

Revision 42014-01-07 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Hardware
  • Electrical
    • Single Board Controller
Added:
>
>
 
      • Clock Driver
        • %TWISTY{mode="div" showlink="Clock Driver Schematic " hidelink="Clock Driver Schematic "
showimgleft="/twiki_oir/pub/TWiki/TWikiDocGraphics/toggleopen-small.gif"
Line: 125 to 134
 
          • Test points
          • Diagnostics/Self-Diagnostics
          • Backplane connector pinouts
Changed:
<
<
>
>
    • Chassis
      • Power Supply Board vs. Chassis Power Supply Trade Study
 
Changed:
<
<
          • Full schematic for the power board
>
>
        • Trade off study of power supply board versus power for chassis
        • Board heat transfer and thermal analysis
        • Water cooling of chassis
        • Chassis Power Analysis
        • Chassis Connector Pinouts
        • Chassis Power
 
Line: 155 to 165
 
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
Deleted:
<
<
    • Chassis
      • Chassis Power Connector
      • Chassis Power Analysis
      • Chassis Connector Pinouts
 
  • Mechanical
    • Chassis Design
Line: 167 to 173
 
      • Cooling/Temperature Monitoring of Chassis
      • State of Health Monitoring of Chassis
Changed:
<
<
Software
>
>
Host Software
 
  • Communication
    • Firmware for USB chipset
    • Communication Protocol

Revision 32014-01-06 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Line: 6 to 6
 
  • Electrical
    • Single Board Controller
      • Clock Driver
Changed:
<
<
        • Clock Driver Schematic (All unique channels)
        • Clock Driver Design Document
>
>
 
          • Rail Noise Analysis
          • Switching Speed Analysis
          • Driving Current and Load Analysis
Line: 15 to 20
 
          • Clock Driver Filter Design
          • Clock Driver Amplifier Design
          • Power Supply Noise Requirements (PSRR Analysis)
Changed:
<
<
        • Clock Driver Power Analysis
>
>
 
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Bias Voltages
Changed:
<
<
        • Bias Voltages Schematic (All unique channels)
        • Bias Voltages Design Document
>
>
 
          • Voltage Noise Analysis
          • Driving Current and Load Analysis
          • Bias Voltage Resolution
          • Bias Filter Design
          • Bias Voltage Amplifier Design
          • Power Supply Noise Requirements (PSRR Analysis)
Changed:
<
<
        • Bias Voltages Power Analysis
>
>
 
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Analog Signal Chain
Changed:
<
<
        • Analog Signal Chain Schematic (All unique channels)
        • Analog Signal Chain Design Document
>
>
 
          • Signal Chain Amplifier Design
          • Signal Chain Noise Analysis
          • Signal Chain Voltage Offset Noise Analysis
Line: 44 to 63
 
          • ADC Communications/Digital Interface
          • Grounding Scheme (mixed-signal ground plane analysis)
          • Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis)
Changed:
<
<
        • Analog Signal Chain Power Analysis
>
>
 
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • FPGA
Changed:
<
<
        • FPGA Schematic and Pinouts
        • FPGA Design Document
>
>
 
          • FPGA Core Firmware
          • FPGA Synchronization
          • FPGA Programmability/Diagnostic Outputs
Line: 58 to 84
 
          • ADC Interface
          • Clock Driver Interface
          • DAC Interface
Changed:
<
<
        • FPGA Power Analysis
>
>
 
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Communications
Changed:
<
<
        • Communication Hardware Schematic
        • Communication Design Document
>
>
 
          • USB Communication Chipset
          • Fiber Optic Chipset
          • Communication/FPGA Interface
Line: 73 to 107
 
          • Power Dissipation
          • Heat Sink Design (if necessary)
      • Single Board Controller
Changed:
<
<
        • Single Board Controller Complete Schematic
        • Single Board Controller Power Analysis
>
>
 
          • SBC Board Power Dissipation
          • Thermal Analysis/Hotspots
          • Heat Sink Design (if necessary)
Changed:
<
<
        • Single Board Controller Design Document
>
>
 
          • Total numbers of functional blocks (i.e. clocks, biases, signal chains)
          • Ejector Hardware/Front plate
          • Test points
          • Diagnostics/Self-Diagnostics
          • Backplane connector pinouts
Changed:
<
<
        • Single Board Controller Layout Document
>
>
 
          • Functional block placement (clock functions, bias functions, and signal chain)
          • Ground plane layout and analysis
    • Power Supply Board
Changed:
<
<
      • Power Board Schematic
      • Power Board Design Document
>
>
 
        • Voltage/Current Requirements
        • Voltage Noise Requirements
        • Thermal Analysis
Line: 97 to 145
 
        • Heat Sink/Thermal Management/Active Cooling
        • Connector Pinouts
    • Backplane
Changed:
<
<
      • Backplane Schematic
      • Backplane Design Document
>
>
 
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
Line: 126 to 179
 
    • Waveform Creator Software
    • Waveform Loader Software
  • Host Computer Code
Changed:
<
<
    • Command Line Library
>
>
 
      • DAC Commands
      • Bias Commands
      • Clock Commands
Line: 139 to 194
 
User Manuals
  • Observer Use
    • GUI Description and Use
Changed:
<
<
    • Image File Format Document
>
>
 
      • Header Data
      • Compression Algorithm
      • Interlacing/De-Interlacing Protocol

Revision 22014-01-02 - StephenKaye

Line: 1 to 1
 
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Hardware
Changed:
<
<
  • Electrical
    • Single Board Controller
      • Single Board Controller Complete Schematic
      • Clock Driver
        • Clock Driver Schematic (Single Channel and/or all unique channels)
        • Clock Driver Design Document
        • Clock Driver Power Analysis
      • Analog Signal Chain
        • Analog Signal Chain Schematic
        • Analog Signal Chain Design Document
        • Analog Signal Chain Power Analysis
      • FPGA
        • FPGA Schematic
        • FPGA Design Document
        • FPGA Power Analysis
    • Power Supply Board
    • Backplane
      • Backplane Schematic
      • Backplane Design Document
      • Backplane Connector Pinouts

  • Mechanical
    • Chassis Design
      • Solidworks drawing of Chassis
      • Mounting points of Chassis
      • Cooling/Temperature Monitoring of Chassis
>
>
  • Electrical
    • Single Board Controller
      • Clock Driver
        • Clock Driver Schematic (All unique channels)
        • Clock Driver Design Document
          • Rail Noise Analysis
          • Switching Speed Analysis
          • Driving Current and Load Analysis
          • Rail Voltage Resolution
          • Clock Driver Filter Design
          • Clock Driver Amplifier Design
          • Power Supply Noise Requirements (PSRR Analysis)
        • Clock Driver Power Analysis
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Bias Voltages
        • Bias Voltages Schematic (All unique channels)
        • Bias Voltages Design Document
          • Voltage Noise Analysis
          • Driving Current and Load Analysis
          • Bias Voltage Resolution
          • Bias Filter Design
          • Bias Voltage Amplifier Design
          • Power Supply Noise Requirements (PSRR Analysis)
        • Bias Voltages Power Analysis
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Analog Signal Chain
        • Analog Signal Chain Schematic (All unique channels)
        • Analog Signal Chain Design Document
          • Signal Chain Amplifier Design
          • Signal Chain Noise Analysis
          • Signal Chain Voltage Offset Noise Analysis
          • Signal Chain Filter Design
          • ADC Biasing Scheme
          • ADC Anti-Aliasing Filter
          • ADC Communications/Digital Interface
          • Grounding Scheme (mixed-signal ground plane analysis)
          • Power Supply Noise Analysis (PSRR Analysis and ADC bias analysis)
        • Analog Signal Chain Power Analysis
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • FPGA
        • FPGA Schematic and Pinouts
        • FPGA Design Document
          • FPGA Core Firmware
          • FPGA Synchronization
          • FPGA Programmability/Diagnostic Outputs
          • USB Communication Interface
          • ADC Interface
          • Clock Driver Interface
          • DAC Interface
        • FPGA Power Analysis
          • Power Dissipation
          • Thermal Analysis
          • Heat Sink Design (if necessary)
      • Communications
        • Communication Hardware Schematic
        • Communication Design Document
          • USB Communication Chipset
          • Fiber Optic Chipset
          • Communication/FPGA Interface
          • Communication Traffic Control
          • Thermal Analysis
          • Power Dissipation
          • Heat Sink Design (if necessary)
      • Single Board Controller
        • Single Board Controller Complete Schematic
        • Single Board Controller Power Analysis
          • SBC Board Power Dissipation
          • Thermal Analysis/Hotspots
          • Heat Sink Design (if necessary)
        • Single Board Controller Design Document
          • Total numbers of functional blocks (i.e. clocks, biases, signal chains)
          • Ejector Hardware/Front plate
          • Test points
          • Diagnostics/Self-Diagnostics
          • Backplane connector pinouts
        • Single Board Controller Layout Document
          • Functional block placement (clock functions, bias functions, and signal chain)
          • Ground plane layout and analysis
    • Power Supply Board
      • Power Board Schematic
      • Power Board Design Document
        • Voltage/Current Requirements
        • Voltage Noise Requirements
        • Thermal Analysis
        • Power Dissipation
        • Heat Sink/Thermal Management/Active Cooling
        • Connector Pinouts
    • Backplane
      • Backplane Schematic
      • Backplane Design Document
        • Connector Pinouts
        • Mounting Hardware
        • Test Points
    • Chassis
      • Chassis Power Connector
        • Chassis Power Analysis
      • Chassis Connector Pinouts

  • Mechanical
    • Chassis Design
      • Solidworks drawing of Chassis
      • Mounting points for Chassis
      • Cooling/Temperature Monitoring of Chassis
      • State of Health Monitoring of Chassis
 
Software
Changed:
<
<
  • FPGA Code
    • Clock Driver Schematic Portion
    • Signal Chain Schematic Portion
    • FPGA Schematic Portion
  • Power Supply Board Schematic

User Manuals
  • Waveform Generation
    • Waveform Creator Software
    • Loading Waveform into FPGA
  • Observer Use
    • GUI Description and Use
    • Command Line Library
>
>
  • Communication
    • Firmware for USB chipset
    • Communication Protocol
  • FPGA Code
    • FPGA Core Firmware Document
    • Firmware Updating/Maintenance
  • Waveform Generation
    • Waveform Generation Document
    • Waveform Creator Software
    • Waveform Loader Software
  • Host Computer Code
    • Command Line Library
 
      • DAC Commands
      • Bias Commands
      • Clock Commands
Line: 53 to 136
 
      • Shutter Interface
      • Digital Status Bits
Added:
>
>
User Manuals
  • Observer Use
    • GUI Description and Use
    • Image File Format Document
      • Header Data
      • Compression Algorithm
      • Interlacing/De-Interlacing Protocol
    • Quick-Look Image Software
 

Revision 12014-01-02 - StephenKaye

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="DetectorReadout"

IFPAC System Documentation

Hardware
  • Electrical
    • Single Board Controller
      • Single Board Controller Complete Schematic
      • Clock Driver
        • Clock Driver Schematic (Single Channel and/or all unique channels)
        • Clock Driver Design Document
        • Clock Driver Power Analysis
      • Analog Signal Chain
        • Analog Signal Chain Schematic
        • Analog Signal Chain Design Document
        • Analog Signal Chain Power Analysis
      • FPGA
        • FPGA Schematic
        • FPGA Design Document
        • FPGA Power Analysis
    • Power Supply Board
    • Backplane
      • Backplane Schematic
      • Backplane Design Document
      • Backplane Connector Pinouts

  • Mechanical
    • Chassis Design
      • Solidworks drawing of Chassis
      • Mounting points of Chassis
      • Cooling/Temperature Monitoring of Chassis

Software
  • FPGA Code
    • Clock Driver Schematic Portion
    • Signal Chain Schematic Portion
    • FPGA Schematic Portion
  • Power Supply Board Schematic

User Manuals
  • Waveform Generation
    • Waveform Creator Software
    • Loading Waveform into FPGA
  • Observer Use
    • GUI Description and Use
    • Command Line Library
      • DAC Commands
      • Bias Commands
      • Clock Commands
      • Self-Diagnostics
      • Board Temperature Monitor
      • Exposure Control
      • Shutter Interface
      • Digital Status Bits

-- StephenKaye - 02 Jan 2014

 
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